Silicon wafers used in electronic devices are typically prepared from a single crystal silicon ingot that is first sliced into thin wafers using a diamond saw, lapped to improve flatness, and etched to remove subsurface damage caused by lapping. The silicon wafers are then typically polished in a two-step process to remove nanotopography caused by etching and to achieve the desired thickness before the wafers are acceptable for use in electronic devices.
In the first polishing step, a high removal rate is required, and ideally the nanotopography would not be worsened during this step. Nanotopography is a parameter that measures the front-surface topology of an area and is defined as the deviation of a surface within a spatial wavelength of around 0.2 to 20 mm. Nanotopography differs from surface flatness in that, for nanotopography, the flatness of the wafer surface is measured relative to the wafer surface itself, while for surface flatness, the flatness of the wafer surface is measured relative to a flat chuck used to hold the wafer. Thus, a wafer may have perfect flatness, yet still have nanotopography. If a wafer has surface irregularities on the front and back sides of the wafer, but the front and back surfaces are parallel, the wafer has perfect flatness. However, the same wafer will exhibit nanotopography. Nanotopography bridges the gap between roughness and flatness in the topology map of wafer surface irregularities in spatial frequency.
Conventional polishing compositions for silicon wafers exhibit high removal rates for silicon, but produce increased nanotopography of the silicon wafers. The increased nanotopography puts increased demands on the second, final polishing step to produce silicon wafers suitable for further processing into semiconductor substrates. Thus, there remains a need in the art for improved polishing compositions for silicon wafers.